1. Field of the Invention
The present invention is related to the field of semiconductor device fabrication and more specifically to a semiconductor device and method of forming that device which reduce junction capacitance while maintaining device isolation.
2. Background Information
In the manufacture of semiconductor devices it has become common practice to build devices side by side and stack them one on top of another. As semiconductor devices become more dense, however, there have been increasing problems with keeping one device electrically isolated from another device. When an operating voltage is applied to a junction of a semiconductor device, the operating voltage can create a depletion region next to the junction. The depletion region is formed when the electric field is not zero thereby taking away all the carriers (thus there is a loss of charges) leaving behind only an ionized fixed impurity charge.
So, for example, when an operating voltage is applied to a drain region of a transistor, that operating voltage may cause a depletion region to grow under the gate region of that transistor. If the depletion region under the gate electrode becomes too large then the source region will no longer be isolated from the drain region. Thus, the source region will show a voltage the same as that of the source region. As another example, when there are two semiconductor devices side by side and an operating voltage is applied to both devices, then both devices will be creating depletion regions. Should those depletion regions touch then the devices are no longer electrically isolated. As yet another example, if two devices are close together and an operating voltage is applied to only one of the devices (first device), but the depletion region grows to a point where it is close to the other device (second device), then the current created at the first device may show up across the second device and the devices are no longer electrically isolated.
One prior art method for helping to control the growth of the depletion regions is to dope the wells in which the depletion regions grow. FIG. 1a illustrates the formation of a doped well. For example, a manufacturer may start with a highly doped P-type layer (P.sup.++ layer) 100. On top of P.sup.++ layer 100 an undoped N-type layer (n-well) 110 is deposited. The undoped n-type layer is then implanted with dopants 120 to form a doped N.sup.+ well portion 125, as illustrated in FIG. 1b.
FIG. 1c illustrates a trench 130 formed in the n-well 110. Trench 130 is an isolation trench which isolates one active region from another active region. As illustrated in FIG. 1d, trench 130 has been filled and there is an active region on each side of trench 130. As an example of a semiconductor device, this description illustrates a transistor being formed in the active regions adjacent trench 130. An oxide layer 140 and a polysilicon layer 150 have been deposited and patterned into gate electrodes above n-well 110. Next, the source and drain regions 160 are formed in the n-well 110 adjacent the gate electrodes to complete the transistor, as illustrated in FIG. 1d.
It should be noted that all the deposition and patterning processes of trenches and device layers, such as photoresist masking and etching trench oxide and gate layer, are well known in the art and are therefore not described in detail herein. Additionally, the processes for forming the source and drain regions are also well known in the art and therefore the detail of such processes is not described.
The increased dopants in the n-well 110 decreases the growth of the depletion regions when an operating voltage is applied to one of the junctions of the semiconductor device. However, in order to effectively reduce the growth of depletion regions a high level of doping is required. One problem with high level doping of this prior art approach is that the dopants being implanted 125 can diffuse throughout the n-layer 110 making it hard to control the dopant profile of the well. Thus, you get a higher concentration of dopants at the top of the well but you may also get dopants in the middle and bottom of the well, where dopants may not necessarily be desired.
Another problem with this prior art approach is that there are trade-offs for decreased depletion region growth. For example, the width of the depletion region is inversely proportional to the capacitance of that region, thus smaller depletion regions will cause higher parasitic capacitances. In other words, this prior art technique trades off the electrical isolation for higher parasitic capacitances. Parasitic capacitances reduce the speed of the circuit and degrade performance.
Another prior art technique that is used in combination with the increased dopant technique to try to reduce the problem of increased parasitic capacitance is the use of a deep retrograde well and a compensation implant. A deep retrograde well is so named because the doping density peaks deep inside the silicon and the doping reduces closer to the surface. A compensation implant is used to reduce the effective doping of the well. FIG. 1f illustrates the use of the combination of retrograde wells and compensation implants 170. After the source and drain regions are formed, for example out of P.sup.+ type implants, another dopant implant, for example P type implants, is performed. The set up is such that the P type implant is positioned just below the source and/or drain regions near the trench 130. This technique helps to alleviate some of the problems of parasitic capacitance because the compensation implants are not as highly doped as the source and drain regions or the n-well in those areas.
However, there is still the problem of control when implanting dopants because the dopants may diffuse to other areas or because implant techniques are not perfectly accurate and thus the compensation implant may be placed in the wrong area. The addition of the compensation implants also increases process steps and increases manufacturing costs both of which may cause their own host of problems in device fabrication.
Yet another prior art method for improved electrical isolation is to etch the trenches deeper into the well. Such an idea sounds simple enough however the actual process steps to do so are very complex and often cost prohibitive. The more complex the processing the more likely the chances of problems arising during fabrication and the more process steps added the higher the fabrication cost. Additionally, as devices become more dense the trenches will have to become narrower making them harder to etch and even harder to fill. If for example a narrow trench cannot be completely filled voids will form which may cause electrical isolation problems of their own.
Thus, what is needed is a method and structure for wells that control depletion region growth and reduce parasitic capacitances.